This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to a method whereby a selective salicide process forms salicide on exposed logic FET""s, while blocking salicide formation on memory FET""s.
In the fabrication of semiconductor integrated circuits the salicide process is well documented for MOSFET and CMOS device formation. Methods are presented which differ in the number of masking steps and processing steps from the present invention.
U.S. Pat. No. 5,672,527 to Lee teaches a method for fabricating an electrostatic discharge protection circuit. The invention describes a process that features only one photo mask to form ESD protection circuit without the salicide and a LDD, lightly doped drain structure.
U.S. Pat. No. 5,719,079 to Yoo et al describes a salicide process for an embedded logic device. A method forming a local interconnect in an SRAM simultaneously with the formation of a salicide in logic devices is described.
U.S. Pat. No. 5,668,024 to Tsia et al is a method to form CMOS devices with a dual sidewall insulator spacers to reduce salicide bridging, as well as, using these regions for pocket implantation regions. The pocket implantation regions are used to reduce punch-through leakage.
U.S. Pat. No. 5,510,648 to Davies et al shows a process for forming salicide with a gate and insulating sidewall spacers of oxide, nitride. The patent teaches that the insulated gate device formed is well suited for the design of low voltage circuits due to the small variations of threshold voltage.
U.S. Pat. No. 4,912,061 to Nasr teaches a method of fabricating CMOS devices using salicide process using a disposable silicon nitride spacer, metal silicide and a single implant step for source, drain and gate. Dual sidewall spacers of oxide/nitride are described with the nitride spacer being removed subsequently.
It is a general object of the present invention to provide an improved method of forming an integrated circuit in which a selective salicide process forms salicide on exposed logic FET""s, while blocking salicide forming on memory FET""s. Thus, yielding logic FET""s with robust salicide structures which exhibit highly conductive lines and contacts, while blocking salicide formation on the sensitive memory FET""s which operate at low voltage and have low leakage, shallow junctions. A conformal layer of thick silicon nitride in conjunction with a salicide blockout mask forms robust selective salicide structures. These structures show low leakage and lack the usual problems associated with conventional salicide processing, such as, silicide bridging, xe2x80x9cribbonsxe2x80x9d or xe2x80x9cstringersxe2x80x9d.
In accordance with the present invention, the above and other objectives are realized in the first embodiment of the present invention by using a method of fabricating robust selective, salicide structures using a second thick conformal layer of dielectric which is refractory and can be selectively etched compared with the etch rate of silicon oxide. This thick conformal layer of refractory dielectric forms a salicide mask, whereby logic FET""s receive the salicide process and memory FET""s are protected by the salicide mask. Hence, a selective salicide process is described in the present invention.
The following process information is provided as a background to the present invention. Prior to said second thick conformal layer of refractory dielectric, conventional processing is provided. For example, a first conformal silicon nitride layer is deposited on oxidized polysilicon gate structures. Anisotropically etch of the silicon nitride layer forms sidewall spacers on the sidewalls of said oxidized polysilicon gate structures. Exposed source and drain regions are then ion implanted forming lightly doped source/drain regions underneath the sidewall structures. Rapid thermal annealing activates the ion implanted dopants while limiting diffusion. The said silicon nitride spacers are etched off leaving oxidized polysilicon gate structures with implanted source and drain regions. Both logic and memory FET""s are processed simultaneously at this stage of the process.
In the first embodiment of the present invention, the second thick conformal layer of refractory dielectric material is any material which meets the general requirements for the process. One of the key requirements is that it must have a high etch selectivity to that of silicon dioxide. In the second embodiment the material is listed as thick silicon nitride. This second conformal material protects the memory FET""s from salicidation.
In the second embodiment of the present invention, the above and other objectives are realized by using the method of selective salicide formation by depositing a second conformal thick layer of silicon nitride, in the thickness range of approximately 500 Angstroms to approximately 1500 Angstroms. Said second thick layer of silicon nitride is patterned by photolithography by applying a salicide blockout mask to the memory FET""s. Anisotropic silicon nitride RIE (Reactive Ion Etch) etching forms robust silicon nitride sidewall spacer structures on the sidewalls of the oxidized silicon nitride gate structures. Greater integrity of the sidewall spacer is achieved with the said thick silicon nitride process.
The blockout photolithography mask is subsequently removed by stripping the resist. Salicide formation process is applied by depositing metals, such as, Ti, Ta, Mo, W, Co, Ni, Pd, Pt onto the substrate. Low electrical resistance, good adhesion and low mechanical stress are some of the more desirable properties in choosing which metal to deposit and by what method to deposit the silicide metal. Silicide formation occurs by diffusion of silicon atoms through the polysilicon to the surface where the reaction with the metal occurs. In some instances, a two step RTA, Rapid Thermal Anneal, in an inert atmosphere converts the silicide from C49 crystal structure to the preferred C54 low electrical resistance structure. Salicide formation occurs in the exposed polysilicon areas and at the top of the source/drain areas, hence it is a self-aligned process. Deleterious bridging, which is silicide formation between the polysilicon and closely spaced source/drain regions is prevented by the robust silicon nitride sidewall structures.
The thick silicon nitride, the silicide protection layer and nitride sidewall spacers are subsequently removed by selectively etching the nitride while leaving the oxide layers and salicide layers intact. This is one of the key aspects of the present invention.
The salicide formation takes place on all the exposed silicon surfaces, that is, at the top of the polysilicon gate and in the diffusion regions. However, the silicon nitride spacers that see exposure to the selective salicide processing metal do not react to form silicide.
The silicon oxide loss or recess in the field isolation region is significantly greater for conventional processing. The reason for this is due to fact that the prior art or traditional process etches silicon oxide to form the salicide mask (self-aligned silicide mask). Therefore, the field silicon oxide, is also etched in the traditional process etch. This non-selective etch results in a recess in the field oxide region. These effects expose the silicon at the edge of the active source/drain regions and cause deleterious silicide formation to occur. This results in leakage around the source/drain. The present invention describes a process whereby thick dielectric silicon nitride can be the refractory material that forms the salicide mask and it can be selectively etched compared with silicon oxide. The selectively etch process minimizes the leakage problem.
In addition, after the salicide process is complete, said thick silicon nitride layer can be anisotropically etched to form sidewall spacers on the memory devices.